Volume 18, No. 6, 2021
Application Aware Workload Allocation To Optimize The Performance In Network On Chip Based Manycore Processor
D. Radha , Mushtaq Shaikh , Vamsi Silla , Minal Moharir
Abstract
With the advancement of powerful standalone applications, web applications, mobile applications etc., the demand for multi-core architecture has increased exponentially. In addition, the advances in CMOS technology led today's chip manufacturers to increase the number of processing cores on a chip to improve the overall computation performance. The execution of any application by many cores of the system, may need to communicate with each other during their cache misses. The Network-on-Chip (NOC) based architecture inherently augments the communication between different cores on a chip. Various routing algorithms can facilitate this communication among the cores on NOC. The proposed method focuses on assigning the same application’s instructions to the nearby cores, and as the application is executed within nearby cores, the communication required is within those cores only, which in turn reduces the latency. Adaptive Routing algorithms enhances the performance of communication with less latency. The comparison is carried out on parameters such as average flit latency, average packet latency, total energy, and total average power for three routing algorithms: Mesh _ XY, Odd-Even, Adaptive Odd-Even in a 2-d Mesh topology. These algorithms are implemented and tested in the Gem5 Simulation tool. With the help of SPEC CPU 2006 benchmarks, the experimental study shows that the performance parameters are optimized when an entire application is executed on one quadrant of a topology compared to the random execution of an application's thread on various cores, which are far from each other.
Pages: 1639-1656
Keywords: Manycore architecture, Network on Chip, Adaptive routing algorithms, Latency, Power, Application