Volume 18, No. 6, 2021
Design And Implementation Of 64 Bit High Speed Vedic Multiplier For DSP Applications
Pooja Krishnamurthy Revankar , Dr. H C Hadimani
Abstract
A multiplier is one of the key hardware blocks in most digital signal processing (DSP) systems. Typical DSP applications where a multiplier plays an important role include digital filtering, digital communications and spectral analysis. Many current DSP applications are targeted at portable, battery-operated systems, so that power dissipation becomes one of the primary design constraints. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. This paper implementation forward a high speed Vedic multiplier, which is efficient in terms of speed, making use of Urdhva Tiryagbhyam, a sutra from Vedic Maths for multiplication of partial products. The most important part of this paper is to reduce the power utilization and give high speed. In these work 64 bit multiplications calculations are performed. The synthesized results are implemented on Genus and Innovus tool GDSII files Cadence tools utilizing 45nm innovation of technology. The recreated comes about for proposed 64 bit Vedic multiplier demonstrates a optimized in area and power utilization against other multiplication techniques. The code is written in Verilog and results shows that multiplier implemented using Vedic multiplication is efficient in terms of area, power and speed compared to its implementation using Array and Booth multiplier architectures.
Pages: 4611-4619
Keywords: Vedic Multiplier, Genus, Innovus, cadence, GDSII file