Volume 18, No. 2, 2021
Application of Multilevel Phase Detector for Clock And Recovery Circuits
Deepika Dobhal, Swapnil Kumar, Vinay Kumar, Ms Preeti Chaudhary
Abstract
For clock and data recovery circuits that are half-rate bang-bang, this article suggests a phase detector (HR-BB-PD) with a number of decision levels. By combining these two methods, the oscillator can run at a data rate that is half that of the input rate while still displaying the size and direction of the PD inputs phase shift. In comparison to a normal two-levels HR BB PD, there is up to 30% reduced output clock jitter. This is because the oscillator's frequency in the phase locked loop of the clock and data recovery circuit may be adjusted more precisely. This enables a bit error rate reduction of up to 5dB in a 5-Gb/s clock and data recovery circuit. A 28-nm FDSOI CMOS device with a supply voltage of 1 V and average power consumption of under 76 W was used to implement the suggested architecture. Despite the highly exciting outcomes of several PLL-based CDRs that have already proposed multilevel (ML) BB PDs, an HR system necessitates a specific PD design. This brief article provides the multi-level (ML-HR-BB-PD).
Pages: 2247-2255
Keywords: CDR circuits, Multi Level half rate phase detector (ML-HR-PD), PLL, CMOS.